PDSE/3D-FFT on Emerging Architectures
One of the most promising techniques to accelerate FFTs and other computational kernels, is the design and programming of specialized logics in reconfigurable hardware (FPGA). By configuring hardware logics so that each core performs small 3D Discrete Fourier Transform, it is possible to specialize hardware logics for fast computation of 3D FFTs. Reconfigurable hardware is one of the candidate computer architectures for exascale machine and it will be investigated by upcoming Exascale project, including EPiGRAM-HS lead by PDC. We will design and implement 3D FFT using FPGAs and develop an application interface, likely based on OpenCL, to offload 3D FFT computation to FPGAs and handle data movement between host/FPGA memory. This will be led by Gilbert Netzer (PDC) with extensive in FPGAs programming experience. We will also compare the performance of 3D FFTs on FPGAs with other hardware, such as Volta GPUs, and other emerging architectures.